Integrated circuit with borderless contacts
US6515351B2 · kind B2 · utility
4Cited by
28References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a conductive region formed on a semiconductor substrate, a silicate glass layer formed on the conductive region, and an etch stop layer formed on the silicate glass layer. The integrated circuit also includes a borderless contact that is coupled to the conductive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.