Method and circuit for optimizing efficiency in a high frequency switching DC-DC converter
US6515463B2 · kind B2 · utility
13Cited by
1References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A switch control (12) circuit which optimizes the efficiency of a buck or boost converter by eliminating simultaneous conductive states of the main power transistor (16) and the synchronous rectifying transistor (18). Power dissipation of the synchronous rectifying transistor (18) is minimized by reducing the amount of time (Td1 and Td2) that the intrinsic body diode of transistor (18) conducts current. Charge control circuit (53) is utilized for boost converter operation and charge control circuit (118) is utilized for buck converter operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.