Negative pump regulator using MOS capacitor
US6515903B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for generating a regulated negative charge pump voltage for flash memory operations, wherein a capacitive voltage divider circuit comprising one or more MOS capacitors is configured to respond to the regulated output voltage of a negative charge pump circuit and an output circuit source loading and generate a voltage divider output signal associated therewith. The system also includes an initialization circuit which is configured to precharge the capacitors of the MOS capacitor voltage divider with a reference voltage. The system further includes a bias circuit operable to generate a bias voltage which is used in association with the MOS capacitors to insure they operate above a bias voltage which will maintain a minimum target capacitance within the voltage divider, resulting in a stable target regulation voltage. The negative regulator also includes an output circuit operable to source the negative charge pump output voltage to a supply voltage, and a negative regulator control circuit operably coupled to the initialization circuit and the capacitive voltage divider circuit, and operable to receive the bias circuit voltage and the associated MOS capacitor vo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.