Semiconductor memory device
US6515924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Oct 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory device comprising a command buffer unit for inputting rasb, casb and web of TTL level and buffering to CMOS level, a unit for buffering bank address signal of TTL level to CMOS level, a cas enable bank signal generating unit indicating the enabled bank wherein the CAS is being performed, a precharge interrupt signal generating unit for combining output signals of the command buffer unit to detect precharge command and for comparing output signal of the bank address buffer unit and the inputted enable bank signal and if enabled bank corresponds to the selected bank, generating and latching precharge interrupt signals to master clock and outputting same, and a unit for generating strobe signals operating predecoder to select bank by external cas or internal cas, controlling options by the precharge interrupt signal, thereby reducing signal lines to bank and preventing unnecessary operations of predecoder and reducing power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.