Semiconductor memory having a wide bus-bandwidth for input/output data
US6515927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Feb 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During a read operation, data read from memory cells onto bit lines are amplified simultaneously by sense amplifiers and outputted to the exterior of a memory. In this operation, a data control circuit outputs to the exterior all the data read from the memory cells onto the bit lines and amplified simultaneously by the sense amplifiers. During a write operation, data supplied from the exterior to the bit lines are amplified by the sense amplifiers and written into the memory cells. In this operation, the data control circuit writes into the memory cells all the data inputted from the exterior and amplified simultaneously by the sense amplifiers. Since all the data amplified simultaneously by the sense amplifiers are inputted/outputted from/to the exterior, the data transfer rate of the input/output data can be improved and the power consumption per unit amount of transferred data can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.