HDLC digital data transmission protocol controller
US6516004B1 · kind B1 · utility
2Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An HDLC transmission protocol controller implemented as an integrated circuit that includes an input port receiving data transmitted by time-division multiplexing of basic HDLC messages, a universal synchronous-asynchronous receiver-transmitter USART module, enabling the parallel transmission of basic messages, a sequential storage module for the basic messages transmitted by the USART, and a reading and sequential processing module for the basic messages using serial processing, in accordance with HDLC protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.