Synchronizing data between differing clock domains
US6516362B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Aug 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock. The return register presents the return data at the next read cycle according to the slower clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.