Information processor
US6516407B1 · kind B1 · utility
7Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference condition code COND, a second conditional instruction having a reference flag SF, and an instruction of operation between two selected second condition codes. A VLIW processor comprises a second condition code register file 163, a condition code conversion circuit 12A, and a logic operation circuit 12E for performing a non-Boolean logic operation between two selected second condition codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.