Multi-layer passivation barrier for a superconducting element
US6517944B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/0716
Abstract
A multi-layer passivation barrier (24) for, and a method of, passivating a superconducting layer (22) of a microelectronic device (20). The passivation barrier includes a passivating layer (32) and a barrier buffering layer (30). The passivating layer provides a barrier to moisture, salts, alkali metals and the like located outside the device. The passivating layer also provides a barrier to outdiffusion of oxygen from the superconducting layer. The buffering layer permits oxygen to diffuse therethrough and provides a barrier to prevent diffusion of one or more constituent chemical elements of the passivating layer into the superconducting layer. The method includes the steps of depositing the barrier buffering layer (30) onto the superconducting layer (22) and depositing the passivating layer (32) onto the buffering layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.