Backside IC device preparation process

US6518074B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Hiep V. Nguyen · Fort Mill, US
• Henry Acedo · معلمی نژاد, US
• Smith J. Johnson · Sunnyvale, US
• Kevin Weaver · San Jose, US

Key dates

• Filing date: Sep 28, 2000
• Grant date: Feb 11, 2003
• Expiry date: Sep 28, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2898
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit backside preparation process back-thins a die using a dry etch process. A wet etch process decaps the integrated circuit to expose the die. After polishing, the prepared integrated circuit is ready for a backside debug analysis.