Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6518089B2 · kind B2 · utility
89Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Feb 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.