Anthony L. Coyle
26Patents
9h-index
17Co-inventors
68Inventor score
Filing activity: Dec 19, 1997 → Sep 10, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6541832B2 | Plastic package for micromechanical devices | Electricity | 113 | Expired |
| US6518089B2 | Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly | Electricity | 89 | Expired |
| US6489178B2 | Method of fabricating a molded package for micromechanical devices | Electricity | 74 | Expired |
| US6049129A | Chip size integrated circuit package | Electricity | 65 | Expired |
| US7608484B2 | Non-pull back pad package with an additional solder standoff | Emerging Cross-Sectional Technologies | 38 | Active |
| US7026710B2 | Molded package for micromechanical devices and method of fabrication | Electricity | 28 | Expired |
| US7335536B2 | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | Electricity | 27 | Expired |
| US6858910B2 | Method of fabricating a molded package for micromechanical devices | Electricity | 26 | Expired |
| US6696757B2 | Contact structure for reliable metallic interconnection | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7863098B2 | Flip chip package with advanced electrical and thermal properties for high current designs | Electricity | 8 | Active |
| US6753616B2 | Flip chip semiconductor device in a molded chip scale package | Electricity | 6 | Expired |
| US7256482B2 | Integrated circuit chip packaging assembly | Electricity | 5 | Expired |
| USRE46466E1 | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | General | 4 | Active |
| US6586676B2 | Plastic chip-scale package having integrated passive components | Electricity | 4 | Expired |
| US7476976B2 | Flip chip package with advanced electrical and thermal properties for high current designs | Electricity | 3 | Active |
| US8039956B2 | High current semiconductor device system having low resistance and inductance | Electricity | 3 | Active |
| US8053876B2 | Multi lead frame power package | Electricity | 2 | Active |
| US7084494B2 | Semiconductor package having integrated metal parts for thermal enhancement | Electricity | 2 | Expired |
| US6916689B2 | Plastic chip-scale package having integrated passive components | Electricity | 2 | Expired |
| US8232144B2 | Non-pull back pad package with an additional solder standoff | Emerging Cross-Sectional Technologies | 2 | Active |
| US8053285B2 | Thermally enhanced single inline package (SIP) | Electricity | 1 | Active |
| USRE48420E1 | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | General | 0 | Active |
| US8154117B2 | High power integrated circuit device having bump pads | Electricity | 0 | Active |
| US7488623B2 | Integrated circuit chip packaging assembly | Electricity | 0 | Active |
| USRE46618E1 | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | General | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.