Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration
US6518111B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Dec 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2255
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a collector region of a semiconductor substrate and forming an isolation structure adjacent at least a portion of the collector region. The method also includes forming a gate stack layer adjacent at least a portion of the isolation structure and forming a base region of the semiconductor substrate adjacent at least a portion of the collector region. The base region comprises a base link up region proximate a lateral edge of the base region. A diffusion source layer is formed adjacent at least a portion of the base link up region. The method includes removing a portion of the gate stack layer to form a base electrode adjacent a portion of the base region and a gate electrode spaced apart from the base electrode. The gate electrode is located at a complementary metal oxide semiconductor (CMOS) area of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.