Process for manufacturing an SOI wafer by oxidation of buried channels
US6518147B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Aug 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76208
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process that includes the steps of forming, in a wafer of monocrystalline silicon, first trenches extending between portions of the wafer; etching the substrate to remove the silicon around the first trenches and forming cavities in the substrate; covering the walls of the cavities with an epitaxial growth inhibiting layer; growing a monocrystalline epitaxial layer on top of the substrate and the cavities so as to obtain a monocrystalline wafer embedding buried cavities completely surrounded by silicon; forming second trenches extending in the epitaxial layer as far as the cavities; removing the epitaxial growth inhibiting layer; oxidizing the cavities, forming at least one continuous region of buried oxide; depositing a polysilicon layer on the entire surface of the wafer and inside the second trenches; removing the polysilicon layer on the surface and leaving filling regions inside the second trenches; and oxidizing, on the top, portions of said filling regions so as to form field oxide regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.