Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit
US6518591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/24
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1. The actual devices are then formed using the same or substantially the same process parameters as were used in forming the sacrificial topology of the monitor according to the present invention, thus insuring that properly formed contact holes, via…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.