Semiconductor package with ground projections
US6518660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Dec 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/166
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover the chip; and one or more projections that electrically connect the lid to a plurality of ground patterns. The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form the ground patterns. The chip is bonded on the upper surface of the substrate. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. An electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections are positioned at four corners of a cavity that is formed between the substrate and the lid. The semiconductor package further includes: external connection terminals formed on the lower surface of the substrate and electrically connected to the corresponding substrate pads; and a thermal interface material is interposed between lid and the chip…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.