Electrically porous on-chip decoupling/shielding layer
US6518670B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/711
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines. The resistive stud, the capacitor dielectric, and the intermediate conductor across the capacitor dielectric layer and t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.