Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
US6519204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.