Designing addition circuits
US6519622B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Feb 11, 2003 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2m+1 and for bit lengths n not of a binary order, the number (m+2) of logical stages is nb0=2m+1, where nb0 is the next largest binary order after n.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.