Repackaging semiconductor IC devices for failure analysis

US6521479B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Ray D. Harrison · Garland, US
• Jianbai Zhu · Plano, US
• Kendall S. Wills · Sugar Land, US
• Willmar Subido · Garland, US

Key dates

• Filing date: Jan 11, 2002
• Grant date: Feb 18, 2003
• Expiry date: Jan 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The present invention provides a system and method for preparing semiconductor integrated circuits (“ICs”), particularly ball grid arrays (“BGAs”), quad flat packs (“QFPs”) and dual in line packages (“DIPs”) for failure analysis (“FA”) using a variety of techniques, including emission microscopy (“EM”) and externally induced voltage alteration (“XIVA”). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.