Modification to fill layers for inlaying semiconductor patterns
US6521537B1 · kind B1 · utility
4Cited by
14References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method of fabricating semiconductor chips that includes modifying physical properties of selected deposit fill layers over patterns having up-features and down-features, with fill to be retained in down-features. The modification enhances chemical mechanical polishing rates, or other polishing, of the modified fill layers to reduce dishing of fill material and achieves this without substantially affecting the electrical properties of the final semiconductor chip product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.