Method of integrating substrate contact on SOI wafers with STI process
US6521947B1 · kind B1 · utility
27Cited by
21References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1999 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jan 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.