Mounting structure for semiconductor devices
US6522022B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Nov 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mounting structure for semiconductor devices wherein a plurality of semiconductor devices each comprised of a semiconductor chip carried on a substrate and provided with connection terminals formed in bump shapes on the substrate are stacked in multiple layers in the vertical direction and mounted on a mounting substrate by electrically connecting the adjoining semiconductor devices through the connection terminals, wherein the connection terminals of the adjoining semiconductor devices are arranged to overlap each other and the connection terminals of the adjoining semiconductor devices are arranged to be displaced from each other in planar arrangement, which thereby eases the stress acting on connection terminals when mounting semiconductor devices stacked on a mounting substrate and improves the reliability of connection between the semiconductor devices and mounting substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.