Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US6522580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.