Method of designing a voltage partitioned wirebond package
US6523150B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Feb 18, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of designing voltage partitions in a package for a chip, comprising: determining the current requirements of a chip voltage island comprising a voltage island and power and signal chip pads; computing the voltage drop across power buses in the chip voltage island; assigning additional chip pads to the chip voltage island for use as power pads if the voltage drop is not acceptable; defining a package voltage island, the package voltage island including power and signal package pads; analyzing electrical attributes of a combination of the chip voltage island, the package voltage island and conductive interconnects connecting chip voltage island pads to package voltage island pads; and assigning additional chip pads to the chip voltage island and additional package pads to the package voltage island for use as power pads until the electrical attributes are acceptable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.