Continuous movement scans of test structures on semiconductor integrated circuits
US6524873B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Sep 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2817
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.