Semiconductor device for use in power-switching device and method of manufacturing the same
US6524894B1 · kind B1 · utility
12Cited by
4References
25Claims
0Family size
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Key dates
| Filing date | Feb 15, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/481
Abstract
An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.