Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution
US6524903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76243
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of a semiconductor device calls for forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer with a pocket structure, the device produced by the present method operates in such a way that fluctuations in the threshold voltage are suppressed. Moreover, with a relative increase in the controllable width of a depletion layer, the sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve the switching rate of the MISFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.