Reduction of tungsten silicide resistivity by boron ion implantation
US6524954B1 · kind B1 · utility
1Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing the resistivity in a gate electrode is described. In one embodiment of the present invention, a silicon layer is formed on a substrate. A tungsten silicide layer is then formed on the silicon layer. The tungsten silicide layer is implanted with boron ions and an anneal is performed. The tungsten silicide layer and silicon layer are then patterned to form a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.