Low resistance wiring in the periphery region of displays
US6525342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | May 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136227
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A display device comprises a gate metal and a data metal formed in an array region and in a periphery region outside of the array region of the display device. A planarizing layer is formed over the array region and the periphery region. Vias are patterned into the planarizing layer in the array region and the periphery region to expose portions of at least one of the gate metal and the data metal. A transparent conductor is deposited in the array region and the periphery region. A metal layer is locally deposited over the transparent conductor in selected areas of the periphery region. The metal layer and the transparent conductor are patterned to form an additional wiring level and/or to form connections between the gate metal and the data metal in the periphery region and to form transparent pixel electrodes in the array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.