High withstand voltage insulated gate N-channel field effect transistor
US6525376B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jan 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A high withstand voltage insulated gate N-channel field effect transistor has a P-type semiconductor substrate and an N-type epitaxial layer formed on the semiconductor substrate. An N-type source region having a high concentration is formed on the epitaxial layer. An N-type drain region having a high concentration is formed on the epitaxial layer and is spaced-apart from the source region. A channel forming region is disposed between the source region and the drain region. A gate insulating film is disposed over the source and drain regions and the channel forming region. A gate electrode is formed through the channel forming region and the gate insulating film. An N-type low concentration region is formed between the drain region and the channel forming region. A second insulating film is formed on the low concentration region and has a thickness greater than that of the gate insulating film. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, and the second insulating film. A P-type well layer is formed in a region under the source region and th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.