Low threshold voltage MOS transistor and method of manufacture
US6525377B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Aug 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
Abstract
A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface. A second well region is disposed in the semiconductor substrate below the channel region, the second well region being of the first conductivity type having a second average dopant concentration. A buried electrode region is disposed below the source and drain regions between the second well region and the channel region. The b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.