Semiconductor substrate having an isolation region
US6525393B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor subst…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.