Latch operating with a low swing clock signal
US6525582B2 · kind B2 · utility
0Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Apr 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.