Graphics processor with pipeline state storage and retrieval
US6525737B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/87
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.