Display list processor for decoupling graphics subsystem operations from a host processor
US6525738B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for decoupling graphics operations from a host processor to improve the efficiency of graphics rendering and free the host processor for other essential tasks. A processing system includes a host processor, a memory, a display list processor (DLP), graphics accelerators and display hardware. The host processor builds display lists generated by graphics applications and stores the display lists in the memory. The display lists include hardware function directives and control directives. The DLP accesses the memory to process the display lists, issuing the hardware function directives to the accelerators to generate display data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.