Fifo bus-sizing, bus-matching datapath architecture
US6526470B1 · kind B1 · utility
4Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising (i) one or more input paths, (ii) one or more output paths, and (iii) one or more switch circuits. The switch circuits may be configured to connect one or more of said input paths to one or more of said output data in response to one or more control signals. The present invention may be used to read and/or write data in one or more modes of operation such as 9-Bit Big Endian Write, 9-bit Little Endian Write, 18-bit Big Endian Write, 18-bit Little Endian Write, a 36-bit Write, 9-Bit Big Endian Read, 9-bit Little Endian Read, 18-bit Big Endian Read, 18-bit Little Endian Read, 36-bit Read or other mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.