Method for locating faulty elements in an integrated circuit
US6526546B1 · kind B1 · utility
10Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process for locating defective elements in an integrated circuit. The integrated circuit is modelled in the form of a tree formed of nodes and oriented arcs. Measurements are performed at various nodes of the circuit by applying a sequence of tests at the input of the circuit. The nodes to be tested are determined recursively as a function of the result of the tests previously performed. Each new test node is such that the number of its ancestors is substantially equal to the number of its descendants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.