Method for improving area in reduced programmable logic devices
US6526563B1 · kind B1 · utility
50Cited by
4References
37Claims
0Family size
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Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Feb 25, 2003 |
| Priority date | — |
| Expiry date | Jan 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.