Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
US6528349B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Compliant wafer level packages 10 and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package 10 having a compliant layer 14 and a compliant interconnect 30 passing therein. The compliant interconnects 30 being provided so that electrical and mechanical connections may be supported across the compliant layer 14, and constructed so that stresses related to relative motion between electrical components is accommodated. A method of providing a substrate 10 having a compliant layer 14, the compliant layer 14 having a via 20 that exposes a die pad 12 on the substrate 10. Fabricating a compliant interconnect 30 so that the compliant interconnect 30 contacts the die pad 12. The compliant interconnect 30 constructed so that electrical and mechanical connections may be supported through the compliant layer 14.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.