Process for producing electrical-connections on a semiconductor package, and semiconductor package
US6528407B1 · kind B1 · utility
1Cited by
17References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for producing electrical-connections on a semiconductor package containing an integrated-circuit chip and with an external protective layer having apertures that least partly expose metal electrical-connection regions, and semiconductor package provided with such metal electrical-connections. The apertures having walls are filled with a metal electrical-connection layer covering at least their walls. A metal solder drop is soldered to the connection layer so that it is not in contact with the external protective layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.