Integrated circuit interconnect and method
US6528426B1 · kind B1 · utility
35Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.