Semiconductor device and a method of manufacturing the same
US6528848B1 · kind B1 · utility
23Cited by
5References
50Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.