Semiconductor wafer having regular or irregular chip pattern and dicing method for the same
US6528864B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Dec 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor wafer whose pattern is composed of a plurality of chip areas delimited by a plurality of streets which at least one or more streets are not straight. Those chip areas may be rectangular ones of same or different sizes delimited by streets which are wholly or partly staggered, or ones of different shapes and/or sizes delimited by streets which are bent or curved so that they may separate adjacent chip areas. Such a semiconductor wafer can be separated into chips by: coating one of the opposite surfaces of each semiconductor wafer with a photo-resistive film; exposing the coated surface of the semiconductor wafer to the light to remove the coating area lying on the streets; subjecting the street-exposed wafer surface to chemical etching to make grooves in conformity with the streets; and separating the semiconductor wafer into chips. The separating step may include making grooves deep enough to reach the front side of the wafer by chemical etching or grinding the grooved wafer on its rear side to remove the remaining thickness of the grooved wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.