Wafer testing interposer for a conventional package
US6529022B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Dec 15, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49162
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides a wafer interposer for electrical testing and assembly into a conventional package. The present invention provides an interposer comprising a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch than the first electrical terminals, and they are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathway.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.