Conditional clock gate that reduces data dependent loading on a clock network
US6529044B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.