Stretching, shortening, and/or removing a clock cycle
US6529057B2 · kind B2 · utility
6Cited by
5References
60Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Apr 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor stage in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.