Multi-bit parallel testing for memory devices
US6529428B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells each have the same polarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.