Semiconductor memory device with concurrent refresh and data access operation
US6529434B2 · kind B2 · utility
4Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes bit lines which transfer data of memory cells, a sense amplifier which is connected to the bit lines, and amplifies data on the bit lines that appears in response to an external access, and a latch circuit which is connected to the bit lines, and amplifies and latches data on the bit lines that appears as data to be refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.