Apparatus and method for testing rambus DRAMs
US6530045B1 · kind B1 · utility
31Cited by
5References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1999 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.